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| this is information on a product in full production. may 2014 docid026008 rev 2 1/48 SRC0 smart push-button on/off cont roller with smart reset? and power-on lockout datasheet - production data features ? operating voltage 1.6 v to 5.5 v ? low standby current of 0.6 a ? adjustable smart reset ? assertion delay time driven by external c srd ? power-up duration determined primarily by push-button press ? debounced pb and sr inputs ? pb and sr esd inputs withstand voltage up to 15 kv (air discharge) 8 kv (contact discharge) ? active high or active low enable output option (en or en) provides control of mosfet, dc- dc converter, regulator, etc. ? secure startup, in terrupt, smart reset ? or power-down driven by push-button ? precise 1.5 v voltage reference with 1% accuracy ? industrial operating temperature -40 to +85 c ? available in tdfn12 2 x 3 mm package applications ? wearable ? activity tracker ? smartwatch ? smartglasses tdfn12 table 1. device summary device rst c srd pb / sr en or en int startup process SRC0 open drain (1) 3 3 push-pull open drain (1) pb must be held low until the ps hold (2) confirmation 1. external pull-up resistor needs to be connected to open drain outputs. 2. for a successful startup, the ps hold (power supply hold) needs to be pul led high within specific time, t on_blank . www.st.com
contents SRC0 2/48 docid026008 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 9 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 docid026008 rev 2 3/48 SRC0 list of tables 48 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 4. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 5. dc and ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 6. tdfn12 (2 x 3 mm) package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 7. carrier tape dimensions for tdfn12 (2 x 3 mm) pa ckage . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 8. SRC0 product selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 9. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 list of figures SRC0 4/48 docid026008 rev 2 list of figures figure 1. application hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. basic functionality (option with enable deasserti on after long push) . . . . . . . . . . . . . . . . . . 6 figure 3. basic functionality (option with rst assertion after long push) . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 5. tdfn12 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 6. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 7. successful power-up on SRC0 (pb released prior to t on_blank expiration) . . . . . . . . . . . 14 figure 8. successful power-up on SRC0 (t on_blank expires prior to pb release) . . . . . . . . . . . . . . 15 figure 9. unsuccessful po wer-up on SRC0 (pb released prior to t on_blank ) . . . . . . . . . . . . . . . . . 16 figure 10. unsuccessful power-up on SRC0 (t on_blank expires prior to pb release) . . . . . . . . . . . . 17 figure 11. successful power-up on SRC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. unsuccessful power-up on SRC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 13. power-up on stm660x with voltage dropout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14. pb interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 15. long push, pb pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16. long push, sr pressed first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17. invalid long push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 18. long push (option with rst assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 19. long push (option with enable deassertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 20. undervoltage detected for docid026008 rev 2 5/48 SRC0 description 48 1 description the SRC0 devices monitor the state of connected push-button(s) as well as sufficient supply voltage. an enable output controls power for the application through the mosfet transistor, dc-dc converter, regulator, etc. if the supply voltage is above a precise voltage threshold, the enable output can be asserted by a simple press of the button. factory- selectable supply voltage thresholds are de termined by highly accurate and temperature- compensated references. an interrupt is asserted by pressing the push-button during normal operation and can be used to request a system power-down. the interrupt is also asserted if undervoltage is detected. by a long push of one button (pb ) or two buttons (pb and sr ) either a reset is asserted or power for the application is disabled depending on the option used. the device also offers additional features su ch as precise 1.5 v voltage reference with very tight accuracy of 1%, separate output indica ting undervoltage detecti on and separate output for distinguishing between interrupt by push-button or undervoltage. the device consumes very low current of 6 a during normal operation and only 0.6 a current during standby. the SRC0 is available in the tdfn12 package and is offered in several options among features such as selectable threshold, hysteresis, timeouts, output types, etc. figure 1. application hookup 1. a resistor is required for open drain output type only. a 10 k ? pull-up is sufficient in most applications. 2. capacitor c ref is mandatory on v ref output (even if v ref is not used). capacitor value of 1 f is recommended. 3. for the SRC0 the processor has to confirm the proper power-on during the fixed time period, t on_blank . this failsafe feature prevents the user from turning on the system when there is a faulty power switch or an unresponsive microprocessor. SRC0 (3) pb out v ref vcc lo pb v cc sr gnd int ps hold rst c srd en (en) dc-dc converter, power mosfet, regulator, etc. led r 1 c srd c ref (2) r 3 (1) r 4 (1) am00246v5 baseband rst i/o nmi or int i/o v dd mcu cpu r 5 (1) description SRC0 6/48 docid026008 rev 2 figure 2. basic functionality (option with enable deassertion after long push) 1. for power-up the battery voltage has to be above v th+ threshold. figure 3. basic functionality (option with rst assertion after long push) 1. for power-up the battery voltage has to be above v th+ threshold. figure 4. logic diagram pb sr power-up (1) interrupt (short push) power-down (long push) en int interrupt interrupt am00243v1 pb power-up (1) interrupt (short push) power-down (long push) sr int interrupt interrupt rst am00243bv1 am00236v2 SRC0 rst gnd c srd int ps hold v cc pb out vcc lo v ref en ( en ) sr pb docid026008 rev 2 7/48 SRC0 description 48 figure 5. tdfn12 pin connections table 2. pin descriptions pin n symbol function 1v cc power supply input 2sr smart reset ? button input 3v ref precise 1.5 v voltage reference 4ps hold ps hold input 5c srd adjustable smart reset ? delay time input 6pb push-button input 7vcc lo output for high threshold comparator output (v th+ ) 8pb out status of pb push-button input 9en or en enable output 10 rst reset output 11 int interrupt output 12 gnd ground am00245v1 gnd c srd ps hold v cc en (en) rst int 5 1 4 8 67 9 10 11 12 3 2 pb out sr v ref pb vcc lo description SRC0 8/48 docid026008 rev 2 figure 6. block diagram 1. internal pull-up resistor connected to pb input (see table 5 for precise specifications). 2. optional internal pull-up resistor connected to sr input (see table 5 for precise specifications). 3. internal pull-down resist or is connected to ps hold input only during startup (see figure 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 18 ). v th+ pb en (en) smart logic edge detector debounce srd logic gnd c srd t rec generator int rst ps hold v cc vcc lo v ref glitch immunity pb out am00237v3 1.5 v edge detector debounce glitch immunity + ? v th? + ? sr r pshold (3) v cc v cc r pb r sr (1) (2) docid026008 rev 2 9/48 SRC0 pin descriptions 48 2 pin descriptions v cc - power supply input v cc is monitored during startup and normal oper ation for sufficient voltage level. decouple the v cc pin from ground by placing a 0.1 f capacitor as close to the device as possible. sr - smart reset ? button input this input is equipped with voltage detector wit h a factory-trimmed threshold and has 8 kv hbm esd protection. both pb and sr buttons have to be pressed and held for t srd period so the long push is recognized and the reset is asserted (or the enable output is deasserted depending on the option) - see figure 13 , 14 , and 15 . active low sr input is usually connected to gnd th rough the momentary push-button (see figure 1 ) and it has an optional 100 k ? pull-up resistor. it is also possible to dr ive this input using an external device with either open drain (recommended) or push-pull output. open drain output can be connected in parallel with push-button or other open drain outputs, which is not possible with push-pull output. sr input is monitored for falling edge after power-up and must not be grounded permanently. v ref - external precise 1.5 v voltage reference this 1.5 v voltage reference is specif ied with very tight accuracy of 1% (see table 5 ). it has proper output voltage as soon as the reset output is deasserted (i.e. after t rec expires) and it is disabled when the device enters stan dby mode. a mandatory capacitor needs to be connected to v ref output (even if v ref is not used). capacitor value of 1 f is recommended. ps hold input this input is equipped with a voltage detector wi th a factory-trimmed threshold. it is used to confirm correct power-up of the device (if en or en is not asserted) or to initiate a shutdown (if en or en is asserted). forcing ps hold high during power-up confirms the proper start of the application and keeps enable output asserted. because most proces sors have outputs in high-z state before initialization, an internal pull- down resistor is connected to ps hold input during startup (see figure 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 18 ). forcing the ps hold signal low during normal operation deasserts the enable output (see figure 12 ). input voltage on this pin is compared to an accurate voltage reference. c srd - smart reset ? delay time input a capacitor to ground determines the additional time (t srd ) that pb with sr must be pressed and held before a long push is recognized. the connected c srd capacitor is charged with i srd current. additional smart reset ? delay time t srd ends when voltage on the c srd capacitor reaches the v srd voltage threshold. it is recommended to use a low esr capacitor (e.g. ceramic). if the capacitor is not used, leave the c srd pin open. if no capacitor is connected, there is no t srd and a long push is recognized right after t int _min expires (see figure 18 and 19 ). pin descriptions SRC0 10/48 docid026008 rev 2 pb - power on switch this input is equipped with a voltage detector with a factory-trimmed threshold and has 8 kv hbm esd protection. when the pb button is pressed and held, the battery voltage is detected and en (or en ) is asserted if the battery voltage is above the threshold v th+ during the whole t debounce period (see figure 13 ). a short push of the push-button during normal operation can initiate an interrupt through debounced int output (see figure 14 ) and a long push of pb and sr simultaneously can either assert reset output rst (see figure 18 ) or deassert the en or en output (see figure 19 ) based on the option used. note: a switch to gnd must be connected to this input (e.g. mechanical push-button, open drain output of external circuitry, etc.), see figure 1 . this ensures a proper startup signal on pb (i.e. a transition from full v cc below specified v il ). pb input has an internal 100 k ? pull-up resistor connected. vcc lo - high threshold detection output during power-up, vcc lo is low when v cc supply voltage is below the v th+ threshold. after successful power-up (i.e. during normal operation) vcc lo is low anytime undervoltage is detected (see figure 13 ). output type is active low and open drain by default. open drain output type requires a pull- up resistor. a 10 k ? is sufficient in most applications. vcc lo is floating when SRC0 is in standby mode. pb out - pb input state if the push-button pb is pressed, the pin stays low during the t debounce time period. if pb is asserted for the entire t debounce period, pb out will then stay low for at least t int _min . if pb is asserted after t int _min expires, pb out will return high as soon as pb is deasserted (see figure 22 ). pb out ignores pb assertion during an undervoltage condition. at startup on the SRC0 pb out will respond only to the first pb assertion and any other assertion will be ignored until t on_blank expires. this output is active low and open drain by default. open drain output type requires a pull-up resistor. a 10 k ? is sufficient in most applications. docid026008 rev 2 11/48 SRC0 pin descriptions 48 en or en - enable output this output is intended to enable system power (see figure 1 ). en is asserted high after a valid turn-on event has been detected and confirmed (i.e. push-button has been pressed and held for t debounce or more and v cc > v th+ voltage level has been detected - see figure 13 ). en is released low if any of the conditions below occur: a) the push-button is released before ps hold is driven high. b) ps hold is driven low during normal operation (see figure 14 ). c) an undervoltage condition is detected for more than t srd + t int _min + t debounce (see figure 21 ). d) a long push of the buttons is detec ted (only for the devi ce with option ?en deasserted by long push? - see figure 19 ) or ps hold is not driven high during t on_blank after a long push of the buttons (only for the device with option ?rst asserted by long push? - see figure 18 ). described logic levels are inverted in case of en output. output type is push-pull by default. rst - reset output this output pulls low for t rec : a) during startup. pb has been pressed (f alling edge on the pb detected) and held for at least t debounce and v cc > v th+ (see figure 7 , 8 , 9 , 10 , 11 , 12 and 13 for more details). b) after long push detection (valid only for the device with option ?rst asserted by long push?). pb has been pressed (f alling edge on the pb detected) and held for more than t debounce + t srd (additional smart reset ? delay time can be adjusted by the external capacitor c srd ) - see figure 18 . output type is active low and open drain by default. open drain output type requires a pull- up resistor. a 10 k ? is sufficient in most applications. int - interrupt output while the system is under normal operation (ps hold is driven high, power for application is asserted), the int is driven low if: a) v cc falls below v th- threshold (i.e. undervoltage is detected - see figure 20 and 21 ). b) the falling edge on the pb is detected and the push-button is held for t debounce or more. int is driven low after t debounce and stays low as long as pb is held. the int signal is held high during power-up. the state of the pb out output can be used to determine if the interrupt was caused by either the assertion of the pb input, or was due to the detec tion of an undervoltage condition on v cc . int output is asserted low for at least t int _min . output type is active low and open drain by default. open drain output type requires a pull- up resistor. a 10 k ? is sufficient in most applications. gnd - ground operation SRC0 12/48 docid026008 rev 2 3 operation the SRC0 simplified smart push-button on/off controller with smart reset ? and power-on lockout enables and disables power for the application depending on push-button states, signals from the processor, and battery voltage. power-on because most of the processors have outputs in high-z state before initia lization, an internal pull-down resistor is connected to ps hold input during startup (see figure 7 , 8 , 9 , 10 , 11 , 12 , 13 , and 18 ). to power up the device the push-button pb has to be pressed for at least t debounce and v cc has to be above v th+ for the whole t debounce period. if the battery voltage drops below v th+ during the t debounce , the counter is reset and starts to count again when v cc > v th+ (see figure 13 ). after t debounce the enable signal is as serted (en goes high, en goes low), reset output rst is asserted for t rec and then the startup routine is performed by the processor. during initialization, the processor sets the ps hold signal high. on the SRC0 the ps hold signal has to be set high prior to push-button release and t on_blank expiration, otherwise the enable sig nal is deasserted (en goes low, en goes high) - see figure 7 , 8 , 9 , and 10 . the time up to push-button release represents the maximum time allowed for the system to powe r up and initialize the circuits driving the ps hold input. if the ps hold signal is low at push-button release, the enable output is deasserted immediately, thus turning off the system power. if t on_blank expires prior to push-button release, the ps hold state is checked at its expi ration. this sa fety feature disables the power and prevents discharging the battery if the push-butto n is stuck or it is held for an unreasonable period of time and the application is not responding (see figure 8 and 10 ). pb status, int status and v cc undervoltage detection are not monitored until power-up is completed. push-button interrupt if the device works under normal operation (i.e. ps hold is high) and the push-button pb is pressed for more than t debounce , a negative pulse with minimum t int _ min width is generated on the int output. by connecting int to the processor interrupt input (int or nmi ) a safeguard routine can be performed and the power can be shut down by setting ps hold low - see figure 14 . forced power-down mode the ps hold output can be forced low anytime duri ng normal operation by the processor and can deassert the enable signal - see figure 14 . undervoltage detection if v cc voltage drops below v th- voltage threshold during normal operation, the int output is driven low (see figure 20 and figure 21 ). if an undervoltage condition is detected for t debounce + t int _min + t srd , the enable output is deasserted (see figure 21 ). hardware reset or power-down while system not responding docid026008 rev 2 13/48 SRC0 operation 48 if the system is not responding and the system hangs, the pb and sr push-button can be pressed simultaneously longer than t debounce + t int _min + t srd , and then a) either the reset output rst is asserted for t rec and the processor is reset (valid only for the device with option ?rst asserted by long push?) ? see figure 18 b) or the power is disabled by en or en signal (valid only for the device with option ?en deasserted by long push?) ? see figure 19 the t srd is set by the external capacitor connected to the c srd pin. sr input is monitored for falling edge after power-up and must not be grounded permanently. standby if the enable output is deasserted (i.e. en is low or en is high), the stm660x device enters standby mode with low current consumption (see table 5 ). in standby mode pb input is only monitored for the falling edge. th e external 1.5 v voltage refe rence is also disabled in standby mode. waveforms SRC0 14/48 docid026008 rev 2 4 waveforms figure 7. successful power-up on SRC0 (pb released prior to t on_blank expiration) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k ? is connected to ps hold input during power-up. 3. en signal is high even after pb release, because processor sets ps hold signal high before pb is released. ps hold ignored internal pull-down resistor connected to ps hold input v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce t rec processor sets ps hold pb released prior to t on_blank expiration ps hold state detected as high en remains asserted t on_blank am00247v3 int signal is held high during power-up (i.e. until pb release in this case). v cc is considered v cc > v th+ . note: docid026008 rev 2 15/48 SRC0 waveforms 48 figure 8. successful power-up on SRC0 (t on_blank expires prior to pb release) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k ? is connected to ps hold input during power-up. 3. t on_blank expires prior to pb release so ps hold is checked at its expiration. ps hold ignored internal pull-down resistor connected to ps hold input v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce t rec processor sets ps hold pb released t on_blank t on_blank expired prior to pb release ps hold state detected as high en remains asserted am00247bv2 int signal is held high during power-up (i.e. until t on_blank expires in this case). v cc is considered v cc > v th+ . note: waveforms SRC0 16/48 docid026008 rev 2 figure 9. unsuccessful power-up on SRC0 (pb released prior to t on_blank ) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k ? is connected to ps hold input during power-up. 3. en signal goes low with pb release, because proc essor did not force ps hold signal high. internal pull-down resistor connected to ps hold input ps hold ignored pb status ignored v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce pb released ps hold state detected as low en deasserted t rec t en_off t on_blank am00248v3 int signal is held high during power-up (i.e. until pb release in this case). v cc is considered v cc > v th+ . note: docid026008 rev 2 17/48 SRC0 waveforms 48 figure 10. unsuccessful power-up on SRC0 (t on_blank expires prior to pb release) 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k ? is connected to ps hold input during power-up. 3. t on_blank expires prior to pb release so ps hold is checked at its expiration. internal pull-down resistor connected to ps hold input ps hold ignored pb status ignored v cc undervoltage detection ignored pb (1) ps hold (2) en (3) rst push-button pressed and pb connected to gnd t debounce pb released t rec t en_off t on_ blank t on_blank expired prior to pb release ps hold state detected as low en is deasserted am00248bv2 int signal is held high during power-up (i.e. until t on_blank expires in this case). v cc is considered v cc > v th+ . note: waveforms SRC0 18/48 docid026008 rev 2 figure 11. successful power-up on SRC0 1. pb detection on falling edge. 2. internal pull-down resistor 300 k ? is connected to ps hold input during power-up. 3. ps hold signal is ignored during t on_blank . when t on_blank expires, the level of the ps hold signal is high therefore the en signal remains asserted. pb status and v cc undervoltage ignored pb (1) en (3) rst push-button pressed and pb connected to gnd t debounce t rec processor sets ps hold detection t on_blank ps hold ignored t on_blank expires ps hold state detected as high en remains asserted (2) internal pull-down resistor connected to ps hold input ps hold am00250v2 int signal is held high during power-up (i.e. until t on_blank expires in the case of the stm6601). v cc is considered v cc > v th+ . note: docid026008 rev 2 19/48 SRC0 waveforms 48 figure 12. unsuccessful power-up on SRC0 1. pb detection on falling edge. 2. internal pull-down resistor 300 k ? is connected to ps hold input during power-up. 3. ps hold signal is ignored during t on_blank . when t on_blank expires, the level of the ps hold signal is not high therefore the en signal goes low. even releasing the pb button after the t on_blank will not prevent this. en (3) (2) t on_blank expires ps hold state detected as low en deasserted intenal pull-down resistor connected to ps hold input t debounce push-button pressed and pb connected to gnd push-button pressed and pb connected to gnd t rec pb (1) rst ps hold ignored ps hold am00238v2 int signal is held high during power-up (i.e. until t on_blank expires in the case of the stm6601). v cc is considered v cc > v th+ . note: waveforms SRC0 20/48 docid026008 rev 2 figure 13. power-up on stm660x with voltage dropout 1. pb detection on falling and rising edges. 2. internal pull-down resistor 300 k ? is connected to ps hold input during power-up. 3. int signal is held high during power-up. v cc goes above v th+ and t debounce is counted again v th? v cc under- voltage detected v cc drop v th+ v cc vcc lo pb (1) en t debounce t rec < t on_blank int signal is held high during power-up ps hold (2) rst push-button pressed and pb connected to gnd < t debounce int (3) internal pull-down resistor connected to ps hold input v cc?min am00249v2 docid026008 rev 2 21/48 SRC0 waveforms 48 figure 14. pb interrupt 1. pb detection on falling edge. pb (1) t debounce t int_min t en_off push-button pressed and pb connected to gnd and en is deasserted accordingly pb status ignored v cc undervoltage detection ignored pb status ignored processor sets ps hold low ps hold am00251v2 processor interrupt starts power-down sequence note: v cc is considered v cc > v th+ . waveforms SRC0 22/48 docid026008 rev 2 figure 15. long push, pb pressed first figure 16. long push, sr pressed first pb status ignored pb int push-button pb is pressed t debounce t int_min sr t debounce push-button sr is pressed t srd starts to be counted am00257v1 t srd set by c srd pb status ignored pb int push-button pb is pressed t debounce t int_min sr push-button sr is pressed t srd starts to be counted t srd set by c srd am00258v1 docid026008 rev 2 23/48 SRC0 waveforms 48 figure 17. invalid long push pb status ignored any rising edge will stop t srd to count regardless of glitch immunity am00259v1 pb int push-button pb is pressed t debounce t int_min sr push-button sr is pressed t srd starts to be counted set by c srd < t srd waveforms SRC0 24/48 docid026008 rev 2 figure 18. long push (option with rst assertion) 1. t srd period is set by external capacitor c srd . 2. pb ignored during t int _min . 3. ps hold signal is ignored during t on_blank . its level is checked after t on_blank expires and if it is high the en signal remains asserted, otherwise en goes low. 4. internal pull-down resistor 300 k ? is connected to ps hold input during startup when device is reset. internal pull-down resistor connected to ps hold input ps hold ignored pb status ignored t on _blank t sr d (1) set by c sr d v cc undervoltage detection status ignored pb ps hold (3, 4) int (2) rst push-button pressed and pb connected to gnd t debounce t rec push-button held even after t srd expires therefore rst is asserted int can go high , if pb goes high, but system freezes and processor won?t respond if system freezes, processor won?t respond to any int status change t int _ min t debounce after t on _blank pb is monitored for falling edge t on _ blank expires ps hold state detected as high therefore en remains high sr am00252v3 note: en is high. docid026008 rev 2 25/48 SRC0 waveforms 48 figure 19. long push (option with enable deassertion) 1. t srd period is set by external capacitor c srd . 2. pb ignored during t int _min . 3. after t srd expires en is forced low. pb status ignored pb status ignored v cc undervoltage detection status ignored pb ps hold int (2) en (3) push-button pressed and pb connected to gnd t debounce push-button held even after t srd expires and en is deasserted t int _ min t debounce after t en_off expires pb is monitored for falling edge t en _ off int can go high, if pb goes high, but system freezes and processor won?t respond if system freezes, processor won?t respond to any int status change t srd (1) set by c srd sr am00253v2 waveforms SRC0 26/48 docid026008 rev 2 figure 20. undervoltage detected for docid026008 rev 2 27/48 SRC0 waveforms 48 figure 22. pb out output waveform 1. pulses on pb shorter than glitch immunity are ignored. 2. pulses on pb shorter than t debounce are not recognized by pb out . 3. minimum pulse width on pb out is t int _min . 4. if push-button is held longer than t debounce + t int _min , pb out goes high when the push-button is released. pb (1,2,3,4) docid026008 rev 2 29/48 SRC0 typical operating characteristics 48 figure 25. supply cu rrent vs. supply voltage, normal state figure 26. supply current vs. supply voltage, standby state 0 1 2 3 4 5 6 7 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage, v cc (v) supply current, i cc (a) t a = 85 c t a = 25 c t a = 0 c t a = ?40 c am04703v1 0.0 0.5 1.0 1.5 2.02.53.03.54.04.55.05.5 supply voltage, v cc (v) supply current, i cc (a) t a = 85 c t a = 25 c t a = 0 c t a = ?40 c am04704v1 typical operating characteristics SRC0 30/48 docid026008 rev 2 figure 27. threshold vs. temperature, v th+ = 3.4 v (typ.) figure 28. threshold hysteresis vs. temperature, v hyst = 200 mv (typ.) 3.20 3.25 3.30 3.35 3.40 3.45 3.50 -40-20 0 20406080 temperature, t a (c) threshold, v th+ (v) am04705v1 170 180 190 200 210 220 230 -40 -20 0 20 40 60 80 temperature, t a (c) threshold hysteresis, v htyst (mv) am04706v1 docid026008 rev 2 31/48 SRC0 typical operating characteristics 48 figure 29. debounce period vs. supply voltage figure 30. c srd charging current vs. temperature, v cc = 3.6 v 15 20 25 30 35 40 45 3.5 4 4.5 5 5.5 supply voltage, v cc (v) debounce period, t debounce (ms) t a = 85 c t a = 25 c t a = 0 c t a = ?40 c am04707v1 100 110 120 130 140 150 160 170 180 190 200 -40 -20 0 20 40 60 80 temperature, t a (c) c srd charging current, i srd (na) v cc = 5.5 v v cc = 3.6 v v cc = 2 v am04708v1 typical operating characteristics SRC0 32/48 docid026008 rev 2 figure 31. output low voltag e vs. output low current, t a = 25 c note: characteristics valid fo r all the outputs (en, en , rst, int , pb out and vcc lo ). figure 32. output high voltage vs. output high current, t a = 25 c note: characteristics valid for en and en outputs. 0.00 0.05 0.10 0.15 0.20 0.25 0.30 012345 output low current, i ol (ma) output low voltage, v ol (v) v cc =1.6v v cc =3.6v v cc =5.5v am04709v1 0 0.2 0.4 0.6 0.8 00.511.52 output high current, i oh (ma) output high voltage, v cc - v oh (v) v cc =1.6v v cc =3.6v v cc =5.5v am04710v1 docid026008 rev 2 33/48 SRC0 typical operating characteristics 48 figure 33. output voltage vs. supply voltage, i out = 1 ma, t a = 25 c note: characteristics valid fo r all the outputs (en, en , rst, int , pb out and vcc lo ). figure 34. input voltage vs. temperature note: characteristics valid for pb , sr and ps hold inputs. 0 0.2 0.4 0.6 0.8 1 012345 supply voltage, v cc (v) output voltage, v out (v) am04711v1 0.99 1.00 1.01 1.02 1.03 1.04 1.05 -40 -20 0 20 40 60 80 temperature, t a (c) input voltage, v in (v) v cc = 3.6 v v cc = 5.5 v am04712v1 typical operating characteristics SRC0 34/48 docid026008 rev 2 figure 35. reference output voltage vs. temperature, v cc = 2.0 v note: 1 f capacitor is connected to the v ref pin. figure 36. reference output voltage vs. load current, v cc = 2.0 v, t a = 25 c note: 1 f capacitor is connected to the v ref pin. 1.480 1.485 1.490 1.495 1.500 1.505 1.510 1.515 1.520 -40-20 0 20406080 temperature, t a (c) reference output voltage, v ref (v) i ref = 0 ma i ref = 15 a am04713v1 1 1.1 1.2 1.3 1.4 1.5 1.6 0 50 100 150 200 250 300 load current, i ref (a) reference output voltage, v ref (v) am04714v1 docid026008 rev 2 35/48 SRC0 typical operating characteristics 48 figure 37. reference output voltage vs. supply voltage, t a = 25 c note: 1 f capacitor is connected to the v ref pin. figure 38. reference startup, i ref = 15 f, t a = 25 c note: 1 f capacitor is connected to the v ref pin. 1.480 1.485 1.490 1.495 1.500 1.505 1.510 1.515 1.520 22.533.544.555.5 supply voltage, v cc (v) reference output voltage, v ref (v) i ref = 0 a i ref = 15 a am04715v1 typical operating characteristics SRC0 36/48 docid026008 rev 2 figure 39. reference response to steps on supply voltage, i ref = 15 a, t a = 25 c note: 1 supply voltage goes from 3.6 v to 5.5 v and back to 3.6 v, ramp 1 v / 100 ns. 2 1 f capacitor is connected to the v ref pin. docid026008 rev 2 37/48 SRC0 typical operating characteristics 48 figure 40. reference response to steps in load current, v cc = 3.6 v, t a = 25 c note: 1 supply voltage goes from 0 a to 15 a and back to 0 a, ramp 1 a / 100 ns. 2 1 f capacitor is connected to the v ref pin. maximum ratings SRC0 38/48 docid026008 rev 2 6 maximum ratings stressing the device above the rating listed in table 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in table 4 of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect device reliability. table 3. absolute maximum ratings symbol parameter min. max. unit remarks v cc input supply voltage ?0.3 +7.0 v input voltages on pb , sr , ps hold and c srd ?0.3 v cc + 0.3 v output voltages on en (en ), rst and int ?0.3 v cc + 0.3 v v esd electrostatic protection ?2 +2 kv human body model (all pins) ?8 +8 kv human body model (pb and sr ) v esd electrostatic protection ?1000 +1000 v charged device model v esd electrostatic protection ?200 +200 v machine model v esd point discharge on pb and sr inputs ?8 +8 kv iec61000-4-2 v esd air discharge on pb and sr inputs ?15 +15 kv iec61000-4-2 t a operating ambient temperature ?40 +85 c t stg storage temperature ?45 +150 c t sld (1) lead solder temperature for 10 seconds +260 c ? ja thermal resistance (junction to ambient) +132.4 c/w 1. reflow at peak temperature of 260 c. t he time above 255 c must not exceed 30 seconds. docid026008 rev 2 39/48 SRC0 dc and ac characteristics 48 7 dc and ac characteristics this section summarizes the operating me asurement conditions and the dc and ac characteristics of the de vice. the parameters in table 5 that follow are derived from tests performed under the measurement conditions summarized in table 4 . designers should check that the operating condit ions in their circuit match the operating conditions when relying on the quoted parameters. table 4. operating and ac measurement conditions parameter condition unit v cc supply voltage 1.6 to 5.5 v ambient operating temperature (t a ) ?40 to 85 c input rise and fall times ?? _ 5ns table 5. dc and ac characteristics symbol parameter test condition (1) min. typ. (2) max. unit v cc supply voltage 1.6 5.5 v i cc supply current v cc = 3.6 v, no load 6.0 8.0 a standby mode, enable deasserted, v cc = 3.6 v 0.6 1.0 a v th+ power-on lockout voltage 3.29 3.40 3.51 v v hyst threshold hysteresis 200 mv 500 v th? forced power-off voltage v th+ ? v hyst v t th? undervoltage detection to int delay v cc ?? 2.0 ? v203244ms t on_blank blanking period (3) 1.4 2.2 3.0 s 5.6 8.8 12.0 11.2 17.6 24.0 rst assertion to en (en ) assertion delay during power-up v cc ?? 3.6 v 100 ns pb v il input low voltage v cc ?? 2.0 ? v, enable asserted 0.99 v v ih input high voltage v cc ?? 2.0 ? v, enable asserted 1.05 v t debounc e debounce period v cc ?? 2.0 ? v203244ms r pb internal pull-up resistor v cc = 5.5 v, input asserted 65 100 135 k ? dc and ac characteristics SRC0 40/48 docid026008 rev 2 sr v il input low voltage 0.99 v v ih input high voltage 1.05 v t debounc e debounce period 20 32 44 ms r sr (4) internal pull-up resistor v cc = 5.5 v, input asserted 65 100 135 k ? pb out v ol output low voltage v cc = 2 v, i sink = 1 ma, pb out asserted 0.3 v pb out leakage current v pbout = 3 v, pb out open drain ?0.1 +0.1 a vcc lo v ol output low voltage v cc = 2 v, i sink = 1 ma, vcc lo asserted 0.3 v vcc lo leakage current v vcclo = 3 v, vcc lo open drain ?0.1 +0.1 a ps hold v il input low voltage v cc ?? 2.0 ? v0.99v v ih input high voltage v cc ?? 2.0 ? v1.05 v glitch immunity 1 80 s ps hold leakage current v pshold = 0.6 v ?0.1 0.1 a ps hold to enable propagation delay 30 s r pshold pull-down resistor connected internally during power-up v pshold = 5.5 v 195 300 405 k ? c srd i srd c srd charging current 100 150 200 na v srd c srd voltage threshold v cc = 3.6 v, load on v ref pin 100 k ? and mandatory 1 f capacitor, t a = 25 c 1.5 v t srd additional smart reset ? delay time external c srd connected 10 s/f en, en v ol output low voltage v cc = 2 v, i sink = 1 ma, enable asserted 0.3 v table 5. dc and ac characteristics (continued) symbol parameter test condition (1) min. typ. (2) max. unit docid026008 rev 2 41/48 SRC0 dc and ac characteristics 48 v oh (5) output high voltage v cc = 2 v, i source = 1 ma, enable asserted v cc ? 0.3 v t en_off (6) enable off to enable on v cc ?? 2.0 ? v406488ms en, en leakage current v en = 2 v, enable open drain ?0.1 +0.1 a rst v ol output low voltage v cc = 2 v, i sink = 1 ma, rst asserted 0.3 v t rec rst pulse width v cc ?? 2.0 ? v 240 360 480 ms rst leakage current v rst = 3v ?0.1 +0.1 a int v ol output low voltage v cc = 2 v, i sink = 1 ma, int asserted 0.3 v t int _min minimum int pulse width v cc ?? 2.0 ? v203244ms int leakage current v int = 3 v ?0.1 +0.1 a v ref v ref 1.5 v voltage reference v cc = 3.6 v, load on v ref pin 100 k ? and mandatory 1 f capacitor, t a = 25 c 1.485 ?1% 1.5 1.515 +1% v 1. valid for ambient operating temperature: t a = ?40 to 85 c; v cc = 1.6 v to 5.5 v (except where noted). 2. typical values are at t a = +25 c. 3. this blanking time allows the pr ocessor to start up correctly (see figure 7 , 8 , 9 , 10 , 11 , 12 ). 4. the internal pull-up resistor connected to the sr input is optional. 5. valid for push-pull only. 6. minimum delay time between enable deas sertion and enable reassertion, allowing the application to complete the power- down properly. pb is ignored during this period. table 5. dc and ac characteristics (continued) symbol parameter test condition (1) min. typ. (2) max. unit package mechanical data SRC0 42/48 docid026008 rev 2 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. docid026008 rev 2 43/48 SRC0 package mechanical data 48 figure 41. tdfn12 (2 x 3 mm) package outline table 6. tdfn12 (2 x 3 mm) package mechanical data symbol mm inches min. typ. max. min. typ. max. a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.15 0.20 0.25 0.006 0.008 0.010 d 3.00 bsc 0.118 e 2.00 bsc 0.079 e 0.50 0.020 l 0.45 0.55 0.65 0.018 0.022 0.026 e 12 (d/2xe/2) index area l bottom view 7 pin#1 id 1 b 6 e seating top vi ew a a1 side view plane 2x d (d/2xe/2) index area 0.10 c 0.10 c 0.10 c 0.10 c a b c b a 0.08 c 8070542_a package mechanical data SRC0 44/48 docid026008 rev 2 figure 42. tdfn12 (2 x 3 mm) recommended footprint note: drawing not to scale. $ 0 [ [ [ [ ' l p h q v l r q v p p l q f k h v [ [ [ [ docid026008 rev 2 45/48 SRC0 package mechanical data 48 figure 43. carrier tape for tdfn12 (2 x 3 mm) package t k 0 p 1 a 0 b 0 p 2 p 0 center lines of cavity w e f d top cover tape user direction of feed am03073v1 table 7. carrier tape dimensions for tdfn12 (2 x 3 mm) package package w d e p 0 p 2 fa 0 b 0 k 0 p 1 tunit bulk qty. tdfn12 12.00 0.30 1.50 +0.10/ ?0.00 1.75 0.10 4.00 0.10 2.00 0.10 5.50 0.05 2.30 0.10 3.20 0.10 1.10 0.01 4.00 0.10 0.30 0.05 mm 3000 product selector SRC0 46/48 docid026008 rev 2 9 product selector table 8. SRC0 product selector full part number en or en (1) after long push (2) internal resistor on sr input power-on lockout voltage v th+ (v) forced power-off voltage v th- (v) t on_blank (s) at startup (min.) ft on_blank (s) at reset (min.) top marking (3) SRC0cs25d en rst pull-up 3.40 3.20 11.2 ? cs25 SRC0gs22d (4) en en ? 3.40 3.20 1.4 ? gs22 1. en (or en ) output is push-pull. rst , int , pb out and vcc lo outputs are open drain. 2. after t srd expires through long push, either device reset (rst ) will be activated for t rec (240 ms min.) or the en (or en ) pin will be deasserted. the additional smart reset ? delay time, t srd , can be adjusted by the user at 10 s/f (typ.) by connecting the external capacitor to the c srd pin. 3. where ?p? = assembly plant, ?y? = assembly year (0 to 9) and ?ww? = assembly work week (01 to 52). 4. please contact local st sale s office for availability. docid026008 rev 2 47/48 SRC0 revision history 48 10 revision history table 9. document revision history date revision changes 04-mar-2014 1 initial release. 13-may-2014 2 modified: v th+ values table 5 on page 39 SRC0 48/48 docid026008 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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